| Abstract: |
This paper presents an empirical, data-driven investigation of a novel StrongARM latch-based dynamic comparator designed and characterized in 20 nm CMOS technology. Dynamic comparators are the decision-making core of high-speed analog-to-digital converters (ADCs) and their delay, power, offset, and noise performance directly dictate converter accuracy and throughput. Building on the classical StrongARM regenerative topology, the proposed design introduces optimized transistor sizing, a modified tail-switching scheme, and a redistributed cross-coupled load to jointly reduce propagation delay, dynamic power, and kickback noise while limiting random offset voltage. Empirical characterization was carried out through simulation-based data collection across supply voltage sweeps, clock-frequency sweeps, 1000-run Monte Carlo mismatch analysis, and common-mode voltage sweeps, and the resulting datasets are summarized in five tabulated experiments. Quantitatively, the proposed 20 nm comparator achieves a 28.8% reduction in propagation delay, a 32.4% reduction in average power at 1 GHz, a 33.3% reduction in 3σ input-referred offset, and a 32.4% reduction in peak kickback noise relative to a 28 nm reference StrongARM design. These empirical results are discussed critically against prior published comparator architectures, confirming that node scaling combined with topology-level optimization yields compounding benefits beyond scaling alone. The findings validate the central claim of this study: architectural refinement of the StrongARM comparator at advanced 20 nm nodes provides a favorable, empirically verifiable trade-off among speed, power, and precision suitable for next-generation high-speed, low-power SAR and pipeline ADCs. |
